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Si4770/77-A20
7. I 2 C Control Bus
A serial port slave interface is provided, which allows an external controller to send commands and receive
responses from the Si4770/77-A20.
7.1. I 2 C Device Address Selection
Two device I 2 C addresses are available, allowing up to four Si4770/77-A20 receivers to share the same I 2 C bus.
The 7-bit device address consists of a fixed part (5 MSBs), followed by a programmable 2-bit part. The LSB of the
device address signals whether a read or write I 2 C operation occurs. The voltage on the A0 and A1 pins are used
to set the programmable 2-bit part of the device address. The A0 and A1 pins are tied to ground and are left to float
for address selection. The various I 2 C device addresses can be selected as summarized in Table 18.
7.2. I 2 C Standard Operation
The I 2 C bus interface is provided for configuration and monitoring of all internal registers. The Si4770/77-A20
supports a 7-bit device addressing procedure and is capable of operating at clock rates up to 400 kHz. Individual
data transfers to and from the device are eight bits. The I 2 C bus consists of two wires: a serial clock line (SCL) and
a serial data line (SDA). The device always operates as a bus slave. In order to be active, the I 2 C block requires
that VIO1 and VD supplies be turned on.
A transaction begins with the START condition, which occurs when SDA falls while SCL is high. Next, the user
drives an 8-bit control byte serially on SDA, which is captured by the device on rising edges of SCL. The control
byte consists of a 7-bit device address followed by a read/write bit (read = 1, write = 0). The Si4770/77-A20
acknowledges the control word by driving SDA low on the next falling edge of SCL.
Read and write operations are performed in accordance with the I 2 C bus specification. For write operations, the
host sends an 8-bit data byte on SDA, which is captured by the device on rising edges of SCL. The Si4770/77-A20
acknowledges each data byte by driving SDA low for one cycle, after the next falling edge of SCL. The host may
write any number of data bytes in a single two-wire transaction. The first byte is a command, and the next bytes are
arguments.
For read operations, after the Si4770/77-A20 has acknowledged the control byte, it drives an 8-bit data byte on
SDA, changing the state of SDA after the falling edge of SCL. The host acknowledges each data byte by driving
SDA low for one cycle, after the next falling edge of SCL. If a data byte is not acknowledged, the transaction ends.
The host may read any number of data bytes in a single two-wire transaction. These bytes contain the response
data from the Si4770/77-A20. A 2-wire transaction ends with the STOP condition, which occurs when SDA rises
while SCL is high.
Table 18. I 2 C Device Address Selection
Device Address [6…2] Device Address [1:0]
A1 Voltage
(Pin Connection)
A0 Voltage
(Pin Connection)
44
11000
11000
11000
11000
11
10
01
00
Rev. 0.9
Floating
Floating
GND
GND
Floating
GND
Floating
GND
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